1. Field of the Invention
The present invention relates to semiconductor integrated circuits containing memory arrays, and in preferred embodiments the invention particularly relates to monolithic three-dimensional memory arrays having series-connected memory cells.
2. Description of the Related Art
Recent developments in semiconductor processing technologies and memory cell technologies have continued to increase the density achieved in integrated circuit memory arrays. For example, certain passive element memory cell arrays may be fabricated having word lines approaching the minimum feature size (F) and minimum feature spacing for the particular word line interconnect layer, and also having bit lines approaching the minimum feature width and minimum feature spacing for the particular bit line interconnect layer. Moreover, three-dimensional memory arrays having more than one plane or level of memory cells have been fabricated implementing such so-called 4F2 memory cells on each memory plane. Exemplary three-dimensional memory arrays are described in U.S. Pat. No. 6,034,882 to Johnson, entitled “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication.”
A variety of other memory cells technologies and arrangements are also known. For example, NAND flash and NROM flash EEPROM memory arrays are known to achieve relatively small memory cells. Other small flash EEPROM cells are known which use hot electron programming, such as NROM and floating gate NOR flash memory arrays. Such memory cells are less desirable for a 3D memory because they use many masks to produce a memory layer, and some use relatively high programming currents.
Other known memory structures are taught by U.S. Pat. No. 6,163,048 by R. T. Hirose et al., entitled “Semiconductor Non-volatile Memory Device Having a NAND Cell Structure,” which describes a memory array utilizing silicon/oxide/nitride/oxide/silicon (SONOS) cells arranged in a NAND architecture in crystalline silicon. U.S. Pat. No. 6,005,270 by T. Noguchi et al., entitled “Semiconductor Nonvolatile Memory Device and Method of Production of Same,” describes a memory array utilizing thin-film transistor (TFT) SONOS cells formed on a low-cost substrate such as glass or plastic. U.S. Pat. No. 5,568,421 by S. Aritome, entitled “Semiconductor Memory Device on which Selective Transistors are Connected to a Plurality of Respective Memory Cell Units,” describes a NAND flash memory array having TFT block select devices and bulk silicon flash cell devices. U.S. Pat. No. 5,621,683 by N. D. Young, entitled “Semiconductor Memory with Non-Volatile Memory Transistor,” describes a memory array including TFT memory cells of a dielectric storage type arranged in a configuration other than a NAND architecture.
Despite such progress, memory arrays having even greater density are desirable. In particular, a memory array technology easily fashioned into a three-dimensional memory array is highly desired.